1. Field of the invention
The present invention relates to a semiconductor device and a method for manufacturing the same, and more specifically to a multilayered wiring structure and a process for forming the same.
2. Description of Related Art
With an advanced microfabrication of the semiconductor device, a micro-multilayered wiring is indispensable to form the semiconductor device. An interlayer insulator film in the semiconductor device having the multilayered wiring structure is mainly formed of a silicon oxide film, which has a small dielectric constant and a stable quality, in order to reduce a parasite capacitance between an upper level wiring layer and a lower level wiring layer and between wiring conductors in the same level.
Because of the microfabrication of the semiconductor device, the width of the lower level wiring conductors and the spacing between adjacent wiring conductors are reduced, but in order to avoid an increase of a wiring resistance, it is necessary to ensure some degree of sectional area of the wiring conductor. As a result, an aspect ratio of wiring conductor ("height of wiring conductor" to "width of wiring conductor") and an aspect ratio of inter-wiring spacing ("height of wiring conductor" to "spacing between adjacent wiring conductors") become large. In addition, it is necessary to fill up a spacing between the lower level wiring conductors with the interlayer insulating film so as to planarize a surface of the interlayer insulating film.
Furthermore, when a large step exists on the surface of the interlayer insulating film, in a photolithographic process for forming the upper level wiring conductor, a fine resist pattern cannot be formed because of a shortage of the focus margin, or even if the fine resist pattern could be formed, disconnection of the upper level wiring conductor and/or an unetched remaining wiring material occur because of the large step. Therefore, it is required that the surface of the interlayer insulating film is planar.
In addition, the interlayer insulating film formed on the metal wiring conductor formed of aluminum is required to be formed at a temperature not higher than 450.degree. C.
A spin-on-glass (SOG) process has been generally used as one typical method for forming the interlayer insulating film formed in a micro-multilayered structure formed of the metal wiring material formed of aluminum. However, this SOG has become difficult to uniformly planarize the whole of the semiconductor chip.
Now, the above mentioned situation will be described with reference to FIGS. 1A to 1C, which are diagrammatic partial sectional views of a semiconductor device for illustrating a process of forming a lower level wiring conductor and an upper level wiring conductor, using the SOG film as a planarizing interlayer insulating film. In FIGS. 1A to 1C, an inside of a semiconductor chip as well as an edge zone and a scribing line zone of the semiconductor chip are shown.
As shown in FIG. 1A, a field oxide film 102 is formed on a silicon substrate 101, and a first level interlayer insulating film 103 is formed on the field oxide film 102 by a chemical vapor deposition (CVD) process. This first level interlayer insulating film 103 is formed of a silicon oxide film.
Then, lower level wiring conductors 104, 104A, 104B and 104C are formed on the first level interlayer insulating film 103. The lower level wiring conductors 104 and 104A are formed in the inside of the semiconductor chip, and the lower level wiring conductor 104B is formed in the chip edge zone. These lower level wiring conductors are formed of for example metal aluminum or metal tungsten, and are used as a power supply line, a ground line or a signal line. This figure shows the power supply line or the ground line having a large line width of 20 .mu.m. Similarly, the lower level wiring conductor 104C formed of aluminum or tungsten, is formed in the scribing line zone of the semiconductor chip, and is connected to the silicon substrate 101.
This lower level wiring conductor 104C is indispensable to prevent generation of a channel leak current under the field oxide film, at a periphery of the semiconductor chip. Incidentally, in a DRAM (dynamic random access memory), this lower level wiring conductor 104C is used as a wiring for a substrate potential generation circuit, or a discharge line for an electro-static discharge (ESD).
Thereafter, a second level interlayer insulating film 105 is formed to cover the lower level wiring conductors. This second level interlayer insulating film 105 is formed of a silicon oxide film having a film thickness of about 300 .mu.m deposited by a plasma CVD process.
Furthermore, an SOG film 106+106a is formed on the second level interlayer insulating film 105. This SOG film is formed by spin-coating an SOG coating solution on the second level interlayer insulating film 105, and then, by heat-treating the spin-coated solution for a thermosetting. For example, this SOG film is formed of an organic silica film.
However, if the SOG film is formed as mentioned above, the film thickness of the SOG film is greatly different between the semiconductor chip inside and the semiconductor chip edge zone. For example, if it is so attempted that the SOG film 106 in the semiconductor chip inside has the film thickness of about 300 .mu.m, the SOG fill 106A in the semiconductor chip edge zone becomes 600 .mu.m. The reason for this is that the SOG film is easy to remain on the lower level wiring conductors in the semiconductor chip edge zone because a surface tension. This phenomenon that the SOG film 106A becomes thick in the semiconductor chip edge zone, becomes more remarkable if the line width of the lower level wiring conductor 104B located in the semiconductor chip edge zone becomes large.
Then, a whole surface of the SOG file is etched back by a dry etching. With this etching-back, the SOG film on the lower level wiring conductors 104 and 104A in the semiconductor chip inside are removed as shown in FIG. 1B. However, the SOG film 106 remains between the lower level wiring conductors 104 and 104A. Thus, the interlayer insulating film is planarized.
In the semiconductor chip edge zone, however, the SOG film 106A remains on the lower level wiring conductors 104B and 104C. This is because the film thickness of the SOG film 106A in the semiconductor chip edge zone is larger than that in the semiconductor chip inside, as mentioned above.
Thereafter, a third level interlayer insulating film 107 is formed by a plasma CVD process. This third level interlayer insulating film 107 is formed of a silicon oxide film having a film thickness of about 400 .mu.m. In the semiconductor chip inside, the third level interlayer insulating film 107 is in direct contact with the second level interlayer insulating film 105 on the lower level wiring conductors 104 and 104A. In the semiconductor chip edge zone, on the other hand, a stacked layer composed of the second level interlayer insulating film, the SOG film and third level interlayer insulating film is formed on the lower level wiring conductors 104B and 104C.
Thereafter, as shown in FIG. 1C, through holes 108 and 108A are formed to penetrate through a stacked interlayer insulating film which is formed on the lower level wiring conductors 104 and 104A and which is composed of the second interlayer insulating film 105 and the third interlayer insulating film 107. Simultaneously, a through hole 108B is formed to penetrate through the stacked layer which is formed on the lower level wiring conductor 104B and which is composed of the second level interlayer insulating film, the SOG film and third level interlayer insulating film.
Furthermore, an upper level wiring conductor 109 is formed to connect through the contact hole 108 to the lower level wiring conductor 104. Similarly, upper level wiring conductors 109A and 109B are formed to connect the lower level wiring conductors 104A and 104B, respectively.
As mentioned above, in the prior art technology, the SOG film in the periphery of the semiconductor chip, namely, in the semiconductor chip edge zone, is formed to become thicker than that in the semiconductor chip inside.
Because of this, the following two significant problems have been encountered.
A first problem is that, the upper level wiring conductor is eroded in a connection portion between the lower level wiring conductor and the upper level wiring conductor within the semiconductor chip edge zone, so that an electrical connection between the lower level wiring conductor and the upper level wiring conductor is deteriorated. As a result, reliability of the semiconductor device greatly lowers.
The deterioration of the electrical connection is considered to have been caused as follows: As mentioned above, in the semiconductor chip edge zone, the SOG film remains on the lower level wiring conductor having the large line width. Therefore, the SOG film is exposed at a side wall of the through hole 108B. On the other hand, the SOG film is high in moisture absorption and therefore is easy to contain moisture. The moisture contained in the SOG film will erode the upper level wiring conductor within the through hole 108B, to ultimately cause disconnection of the wiring conductor or elevation of the wiring resistance.
In order to overcome this problem, Japanese Patent Application Pre-examination Publication No. JP-A-5-206284 (the content of the which is incorporated by reference in its entirety into this application, and also an English abstract of JP-A-5-206284 is available from the Japanese Patent Office and the content of the English abstract of JP-A-5-206284 is also incorporated by reference in its entirety into this application) proposes a method in which the SOG film is not exposed at the side wall of the through hole. However, the advantage of this proposed method becomes lost if the line width of the wiring conductor becomes large.
A second problem is that, coverage of the upper level wiring conductor is deteriorated also in the connection portion between the lower level wiring conductor and the upper level wiring conductor within the semiconductor chip edge zone, with the result that the electrical connection becomes difficult.
The reason for this is that: as mentioned above, in the semiconductor chip edge zone, since the SOG film remains on the lower level wiring conductor having the large line width, the through hole 108B becomes deep and therefore, the aspect ratio of the through hole 108B becomes large.